1. Field of the Invention
The present invention relates generally to communication systems of the binary digital type and, more particularly, to a system that prevents spurious input control signals from producing errors in systems using sequential phase detectors in conjunction with phase-locked loop signal processing.
2. Description of the Prior Art
Many communication systems such as, for example, power line carrier systems use digital modulation techniques in signal transmission. Transmission of such signals is controlled by modulating the input to the transmitter system as by impressing on a carrier signal a train of pulses at given frequency intervals to indicate whether a "mark" or binary "1" or a "space" or binary "0" should be transmitted. One such digital transmission technique involves frequency shift keyed (FSK) modulation. This is the type employed in the preferred embodiment of the present invention.
In this type of a system, one frequency is used to indicate a mark and another to indicate a space. Frequency shift keying involves the modulation of the base or carrier frequency to shift its frequency by predetermined increments in response to particular data to be transmitted.
In such a system, the frequency shift phase is continuous, i.e. the transmitted signal is a sinusoidal signal which varies in frequency but has no time-phase shift continuity. Normally, a binary "1" or mark signal is transmitted at a frequency above a selected center frequency or "carrier plus" frequency and a space or binary "0" is transmitted at a frequency below the center frequency of the carrier or "carrier minus" frequency. The differential between a transmitted frequency and the center frequency of the carrier may be made equal to or greater than the modulation rate, or data rate, divided by two.
One well known method of controlling such a system to prevent phase shifting consists of applying the input signal to a phase-locked loop whose output is sampled once every bit period in accordance with a sample control signal which is generated in accordance with the bit period. The phase-locked loop circuit normally consists of a phase detector which compares the frequency of a VCO with that of the incoming control signal or reference-frequency generator. The output of the phase detector, after passing through a loop filter, is fed back to the VCO to keep it exactly in phase with the incoming or reference frequency.
An important component of any phase-locked loop, of course, is the phase detector. Basically, the phase detector provides a direct current output voltage which is related to the phase difference between the oscillator signal phase and that of a reference signal for use in controlling the oscillator to keep it in synchronism with the reference signal. The phase detector is extremely important in maintaining the phase lock to provide proper output from the phase-locked loop.
One important type of phase detector is known as a sequential phase detector. A sequential phase detector is a digital circuit which measures phase differences by observing the sequence of the transitions or "zero" crossings of the input signals. These are normally the leading edge or positive zero crossings. Sequential phase detectors are implemented with bistable elements or flip-flops to "remember the input sequence." Many implementations are possible. One sequential phase detector in common use is known as the sequential phase frequency detector.
Sequential phase detectors have often been used because they have many desirable qualities. They are simply and inexpensively implemented from readily available digital circuits. They can have high gain with very small phase errors. When used in phase-locked loops, they can eliminate the loop "hang-up" problem and provide rapid, reliable phase and frequency acquisition. Because no linear or discrete elements are used in the circuits, sequential phase detectors are particularly attractive for integrated circuit implementations.
However, sequential phase detectors including sequential phase-frequency detectors have one undesirable characteristic. Because these devices are transition operated circuits with memory, they are intolerant of missing or extraneous input transitions due to noise or other spurious signals in the input. Whereas with other types of phase detectors, a small extraneous transient signal will produce but a small transient phase error signal, in the case of a sequential phase detector, such extraneous or transient signals which involve a transition may produce very large error signals. Consequently, in phase-locked loop applications, the effect of noise transitions on a sequential phase detector will normally cause the loop to lose lock. In this situation, it may be many clock periods before the phase-locked loop is able to regain lock.
It can be seen from the above that there exists a need to eliminate the effect of extraneous transitions so that otherwise desirable sequential phase detectors may be used successfully in situations where such transitions often occur. One solution, for example, might be to filter the input signal to remove the spurious transitions. The inherent phase shift of such a filter, however, may also obscure the desired phase relationship. Such filters also normally require discrete components and linear elements which increase the cost and design problems of the associated circuitry and overcome the advantages of using the sequential phase detector in the first place.